The easy jump of one to two bits-per-cell gives a straight 100% increase, in exchange for more control needed to read/write the bit but also limits the cell endurance.
So your AND gate with 3 inverters could be converted to a NOR gate with one inverter on the output - which reduces the number of gates from 4 to 2.One of the key drivers to increase capacity in next generation storage has been to increase the number of bits that can be stored per cell. This is useful when for example you only have NAND gates and need to create a NOR function, or you want to reduce the number of gates in a circuit.Īpplying De Morgan's law will not change positive logic into negative logic, but it helps when you want to invert a lot of signals with the minimum number of gates. However its truth table in positive logic has all the '1's and '0's inverted.ĭe Morgan's law says that an AND gate with inverted output (ie a NAND gate) is equivalent to an OR gate with inverted inputs, and an AND gate with inverted inputs is equivalent to an OR gate with inverted output (ie. That combination is then a negative logic AND gate, and its truth table (in negative logic) is the same as the bare AND gate was in positive logic. So to convert a gate from positive to negative logic you just have to invert (negate) all the signals.įor example if you had a positive logic AND gate that you wanted to use in a negative logic circuit, you would have to put inverters on both the inputs and the output. However if you are changing from positive to negative logic then logic '1' in positive logic translates to logic '0' in negative logic. logic '1' = low voltage and logic '0' = high voltage.Ī truth table only tells you the logic values, not the voltages that produce them. Positive logic assigns logic '1' to high voltage and logic '0' to low voltage.
0 kommentar(er)
